As you come to 52nd DAC looking for new design automation technology and breakthrough solutions, ICSCape welcome you to visit our booth 1602 to see how our EDA and IP solutions can help your design tape-outs and chip finishing.
ICScape EDA solutions solve some crucial SoC design closure issues and boost AMS custom design productivities. ICScape also offers silicon proven IPs for most of commonly used high speed interfaces including SATA, PCIE, USB, DDR, and HDMI/MHL.
The following are product highlights:
SoC Design Closure and Chip Finishing:
- ClockExplorerTM: Analyzes clock structures and optimizes clock constraints for shorter insertion delay. Reduce OCV (On-Chip-Variation) on clock and reduce the TAT (Turn-Around-Time) of timing closure.
- SkipperTM: Large scale layout data processing platform. Reduce TAT of chip finishing and reduce TAT of chip failure analysis.
- TimingExplorerTM: Placement and routing aware MMMC timing closure, Reduce TAT of timing closure
- QualibTM: Library/IP QA and debugging platform. Reduce risk of panic right before tapeout on issues not relevant to designAMS Custom Design Booster:
- RCExplorerTM: Interactive in-design pre-LVS resistance calculation and post extraction R/C calculation. Reduce TAT of chip debugging due to layout parasitic.
- AeolusTM: True SPICE simulator with competitive performance.IP:
- 28nm 12.5Gbps SerDes.
Click HERE for more information.